d a t a sh eet product speci?cation file under integrated circuits, ic06 december 1990 integrated circuits 74hc/hct125 quad buffer/line driver; 3-state for a complete data sheet, please also download: the ic06 74hc/hct/hcu/hcmos logic family specifications the ic06 74hc/hct/hcu/hcmos logic package information the ic06 74hc/hct/hcu/hcmos logic package outlines
december 1990 2 philips semiconductors product speci?cation quad buffer/line driver; 3-state 74hc/hct125 features output capability: bus driver i cc category: msi general description the 74hc/hct125 are high-speed si-gate cmos devices and are pin compatible with low power schottky ttl (lsttl). they are specified in compliance with jedec standard no. 7a. the 74hc/hct125 are four non-inverting buffer/line drivers with 3-state outputs. the 3-state outputs (ny) are controlled by the output enable input (n oe). a high at n oe causes the outputs to assume a high impedance off-state. the 125 is identical to the 126 but has active low enable inputs. quick reference data gnd = 0 v; t amb = 25 c; t r = t f = 6 ns notes 1. c pd is used to determine the dynamic power dissipation (p d in m w): p d = c pd v cc 2 f i + ? (c l v cc 2 f o ) where: f i = input frequency in mhz f o = output frequency in mhz c l = output load capacitance in pf v cc = supply voltage in v ? (c l v cc 2 f o ) = sum of outputs 2. for hc the condition is v i = gnd to v cc for hct the condition is v i = gnd to v cc - 1.5 v ordering information see 74hc/hct/hcu/hcmos logic package information . symbol parameter conditions typical unit hc hct t phl / t plh propagation delay na to ny c l = 15 pf; v cc =5v 9 12 ns c i input capacitance 3.5 3.5 pf c pd power dissipation capacitance per buffer notes 1 and 2 22 24 pf
december 1990 3 philips semiconductors product speci?cation quad buffer/line driver; 3-state 74hc/hct125 pin description pin no. symbol name and function 1, 4, 10, 13 1 oe to 4 oe outputs enable inputs (active low) 2, 5, 9, 12 1a to 4a data inputs 3, 6, 8, 11 1y to 4y data outputs 7 gnd ground (0 v) 14 v cc positive supply voltage fig.1 pin configuration. fig.2 logic symbol. fig.3 iec logic symbol. (a) (b) fig.4 functional diagram. fig.5 logic diagram (one buffer). function table note 1. h = high voltage level l = low voltage level x = dont care z = high impedance off-state inputs output n oe na ny l l h l h x l h z
december 1990 4 philips semiconductors product speci?cation quad buffer/line driver; 3-state 74hc/hct125 dc characteristics for 74hc for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: bus driver i cc category: msi ac characteristics for 74hc gnd = 0 v; t r =t f = 6 ns; c l =50pf symbol parameter t amb ( c) unit test conditions 74hc v cc (v) waveforms +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. t phl / t plh propagation delay na to ny 30 100 125 150 ns 2.0 fig.6 11 20 25 30 4.5 9 17 21 26 6.0 t pzh / t pzl 3-state output enable time n oe to ny 41 125 155 190 ns 2.0 fig.7 15 25 31 38 4.5 12 21 26 32 6.0 t phz / t plz 3-state output disable time n oe to ny 41 125 155 190 ns 2.0 fig.7 15 25 31 38 4.5 12 21 26 32 6.0 t thl / t tlh output transition time 14 60 75 90 ns 2.0 fig.6 5 12 15 18 4.5 4 10 13 15 6.0
december 1990 5 philips semiconductors product speci?cation quad buffer/line driver; 3-state 74hc/hct125 dc characteristics for 74hct for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: bus driver i cc category: msi note to hct types the value of additional quiescent supply current ( d i cc ) for a unit load of 1 is given in the family specifications. to determine d i cc per input, multiply this value by the unit load coefficient shown in the table below. ac characteristics for 74hct gnd = 0 v; t r =t f = 6 ns; c l =50pf input unit load coefficient na, n oe 1.00 symbol parameter t amb ( c) unit test conditions 74hct v cc (v) waveforms +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. t phl / t plh propagation delay na to ny 15 25 31 38 ns 4.5 fig.6 t pzh / t pzl 3-state output enable time n oe to ny 15 28 35 42 ns 4.5 fig.7 t phz / t plz 3-state output disable time n oe to ny 15 25 31 38 ns 4.5 fig.7 t thl / t tlh output transition time 5 12 15 18 ns 4.5 fig.6
december 1990 6 philips semiconductors product speci?cation quad buffer/line driver; 3-state 74hc/hct125 ac waveforms package outlines see 74hc/hct/hcu/hcmos logic package outlines . fig.6 waveforms showing the input (na) to output (ny) propagation delays and the output transition times. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v. fig.7 waveforms showing the 3-state enable and disable times. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v.
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